An FPGA based Hardware Architecture for Golay Code Encoder and Decoder

Dr.P. Rajeswari, K.R.J. Deepica, M. Kanagamani and Blessy Babu


In this paper we presented the FPGA based hardware structure for encoding and decoding of Extended Golay code. Both the encoding and decoding architecture prototype is implemented separately in Virtex-4 FPGA series and found the maximum operating frequency to be 242.32MHz and 202.12MHz respectively. Also the hardware is tested against various link speeds to prove its suitability for real time traffic patterns. The result shows it can support a link rate of 10 Gbps efficiently. Thus the proposed structure ensures a high speed coding and decoding of data for the current link rate demand.

Keywords: Architecture, Field Programmable Gate Array (FPGA), Encoder, Decoder, Golay Code.

Volume: 5 | Issue: 1

Paper ID : IJPPAS105015

Issue Date: February , 2017

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